MWSCAS 2024

IMPORTANT DEADLINE DATES

July 9:
Early Registration and Hotel conference rate reservation deadline.

General Co-Chairs
Neeraj Magotra
Western New England University
neeraj.magotra@wne.edu

Randy Geiger
Iowa State University
r.geiger@ieee.org

August 11th – 14th 2024

IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) 2024 venue is the Sheraton Springfield Monarch Place Hotel.

Registration for MWSCAS 2024 is now open

Get your early registration completed.

CONFERENCE REGISTRATION

Make your hotel reservations early to get special conference room rates.

HOTEL REGISTRATIONS

IEEE CREDIT FOR TUTORIALS!

All tutorial attendees will receive IEEE Credential for 4 Professional Development Hours (PDH)

Call for Papers download

Download Program at a Glance PDF

Distinguished Keynote Speakers

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Circuit Research to Enable Next Generation AI Datacenters

Abstract: AI applications on GPU systems have exploded with an almost unlimited appetite for compute. Single-chip inference performance has increased 1000X over the last 10 years with improvements ranging from architecture to circuits. Tens of thousands of datacenter connected GPUs are needed for training and inference of state-of-the-art generative AI models. Bandwidth density requirements increase on the order of 2x in each generation and power delivery is strained at all levels from on-die to datacenter. This creates a critical need for future research addressing scaling and power reduction in all areas including compute/memory, communication, power delivery, and heat removal. In this talk, we will explore what is ultimately needed for design and deployment of these systems at the circuit and hardware level including circuits for compute, electrical and photonic interconnect, memory system design and scaling, packaging and stacking, power delivery and conversion at the rack, board, and die level, and thermal design and limitations.

C. Thomas Gray received the B.S. degree in computer science and mathematics from Mississippi College, Clinton, MS, USA, and the M.S. and Ph.D. degrees in computer engineering from North Carolina State University, Raleigh, NC, USA. From 1993 to 1998, he was an Advisory Engineer with IBM, Research Triangle Park, NC, USA, working on transceiver design for communication systems. From 1998 to 2004, he was a Senior Staff Design Engineer with the Analog/Mixed Signal Design Group, Cadence Design Systems, working on SerDes system architecture. From 2004 to 2010, he was a Consultant Design Engineer with Artisan/ARM and Technical Lead of SerDes architecture and design. In 2010, he joined Nethra Imaging as a System Architect. His work experience includes digital signal processing design and CMOS implementation of DSP blocks as well as high-speed serial link communication systems, architectures, and implementation. In 2011, he joined NVIDIA, Inc., Durham, NC, USA, where he is currently Senior Director of Circuit Research, leading activities related to high-speed electrical signaling, photonics, power delivery, security circuits, low-energy and resilient memories, circuits for machine learning, and variation-tolerant clocking and power delivery.

Thomas Gray, Ph.D.

Senior Director of Circuit Research, NVIDIA

August 12, 2024

What is Peace Engineering?

Abstract: Peace Engineering is a new emerging field. It is the outcome of the First Global Peace Engineering Conference, WEEF-GEDC-2018, November 2018. Peace Engineering is the intentional application of systemic-level thinking of science, culture, technology and engineering principles to directly promote and support conditions for peace. Peace Engineering works directly towards a world where prosperity, sustainability, social equity, entrepreneurship, transparency, community voice and engagement, ethics and a culture of quality thrive. Engineers have the power to play a vital role in the creative solutions that can radically transform and improve the well-being of people and other living systems, day to day. At the core of Peace Engineering is our planet’s sustainable future, which is calling leaders to act in concert from a systems mindset. It is a call to develop solutions differently: that is, collaboratively; integrating transdisciplinary expertise and education programs; simultaneously applying technology solutions while supporting ethics, policy and living systems. And it is a call in the mingled vernacular of civil society, global institutions, and science and technology. Further, beyond addressing today’s challenges, we must cultivate together the development of next generation leaders to continue to drive momentum.

Ramiro Jordan is a scientist, innovator, educator, and entrepreneur. He is a member of the faculty of the Department of Electrical and Computer Engineering (ECE) at the University of New Mexico. He served and Undergraduate Chair of ECE and Associate Dean of Engineering – Global Initiatives. His research activities include sustainability, Peace Engineering, smart grids, cognitive radio, multidimensional signal processing, and software development. He is the founder of the Ibero-American Consortium for Science and Technology Education (ISTEC, Inc.), December 1990, a successful non-profit organization that was created with the mission to accelerate STEM education, technological, socio-economic development, R&D and entrepreneurship in Latin America and the Iberian Peninsula. He is past president of the International Federation of Engineering Education Societies (IFEES), Nov. 2018-2020. He is a founding member of the Peace Engineering Consortium, outcome of the first global conference on Peace Engineering, WEEF-GEDC Nov. 2018, Albuquerque, NM. He is bestowed with the Order of Rio Branco, in the rank of Officer, by the Brazilian Government.

Ramiro Jordan, Ph.D.

Professor, University of New Mexico

August 13, 2024

Challenges and opportunities for ultra-low power design for quantum computing applications

Abstract: This talk will cover practical challenges for cryogenic CMOS designs for next generation quantum computing. Starting from system level, it will detail the design considerations for a non-multiplexed, semi-autonomous, transmon qubit state controller (QSC) implemented in 14nm CMOS FinFET technology. The QSC includes an augmented general-purpose digital processor that supports waveform generation and phase rotation operations combined with a low power current-mode single sideband upconversion I/Q mixer-based RF arbitrary waveform generator (AWG). Implemented in 14nm CMOS FinFET technology, the QSC generates control signals in its target 4.5GHz to 5.5 GHz frequency range, achieving an SFDR > 50dB for a signal bandwidth of 500MHz. With the controller operating in the 4K stage of a cryostat and connected to a transmon qubit in the cryostat’s millikelvin stage, measured transmon T1 and T2 coherence times were 75.5μS and 73 μS, respectively, in each case comparable to results achieved using conventional room temperature controls. In further tests with transmons, a qubit-limited error rate of 7.76x10-4 per Clifford gate is achieved, again comparable to results achieved using room temperature controls. The QSC’s maximum RF output power is -18 dBm, and power dissipation per qubit under active control is 23mW.

Sudipto Chakraborty (B. Tech, IIT, Kharagpur, 1998, Ph.D from Georgia Tech, 2002) was with Texas Instruments till 2016 where he designed low power IC for >10 product families in automotive/wireless/medical/microcontrollers. Since 2017 he led the low power circuit design for next generation quantum computing applications in IBM research using nanometer CMOS. He has authored or co-authored >80 papers, two books and 90 US patents. He has served in the TPC including ISSCC, CICC, RFIC, IMS, and is an IBM master inventor in 2022. He serves as an AE of the (TCAS – I) and distinguished lecturer in the IEEE CASS and SSCS.

Sudipto Chakraborty, Ph.D.

IBM T. J. Watson Research Center

August 14, 2024

Program at a glance